Non-volatile memory storage transistors are well known in the art. In particular a non-volatile memory storage transistors using a floating gate to store charges thereon which control the conduction of the channel region over which the floating gate is positioned is well known in the art. Referring to FIG. 1 there is shown a cross-sectional view of a non-volatile memory storage transistor 10 of the prior art. Such a storage transistor 10 is fully disclosed in U.S. Pat. No. 5,029,130 whose disclosure is incorporated in its entirety.
The storage transistor 10 comprises a substrate 12 of a first conductivity type, such as P type. A first region 14 and a second region 16 each of a second conductivity type is in the substrate 12 spaced apart from one another by a channel region 18. A floating gate 22 is over a portion of the channel region 18 and is insulated therefrom by an insulator. The floating gate 22 is also over a portion of the first region 14 and is capacitively coupled thereto, as disclosed in U.S. Pat. No. 5,029,130. A control gate 29 is adjacent to the floating gate 22, spaced apart therefrom, and controls the conduction of current in another portion of the channel region 18. The control gate 29 is capacitively coupled to the floating gate 22. In the operation of the storage transistor 10, during programming, a first current (or programming current) is applied to the second region 16, while during a read operation, a first voltage (read voltage) is applied to the second region 16. However, during programming, electrons from the second region 16 travel to the first region 14, and are injected onto the floating gate 22. Some electrons may be trapped at the insulator interface between the floating gate 22 and the substrate 12. Over time, this degrades the floating gate transistor transconductance and degrades the endurance of the storage transistor 10.
Referring to FIG. 2 there is shown a schematic view of an array of storage transistors 10. Referring to FIG. 3 there is shown a top view of an array of the storage transistors 10 of the prior art.
Referring to FIG. 4, there is shown a cross sectional view of another storage transistor 50 of the prior art. The storage transistor 50 is fully disclosed in U.S. Pat. No. 6,747,310 whose disclosure is incorporated herein in its entirety by reference. The storage transistor 50 is similar to the storage transistor 10. The storage transistor 50 comprises a substrate 12 of a first conductivity type, such as P type. A first region 34 and a second region 36 each of a second conductivity type is in the substrate 12 spaced apart from one another by a channel region 39. A floating gate 31 is over a portion of the channel region 39 and is insulated therefrom. A select gate 33 is adjacent to the floating gate 31, spaced apart therefrom, and controls the conduction of current in another portion of the channel region 39. The select gate 33 is capacitively coupled to the floating gate 31. In addition, a control gate 32 is on top of the floating gate 31. Finally, an erase gate 35 is over the first region 34, and is adjacent to the floating gate 31 on a side opposite to the select gate 33. Similar to the operation of the storage transistor 10 in the operation of the storage transistor 50, during programming, a first current (or programming current) is applied to the second region 36, while during a read operation, a first voltage (read voltage), is applied to the second region 36. Similar to the storage transistor 10, during programming, program disturbance may degrade the endurance of the storage transistor 50.
Hence it is one object of the present invention to reduce the affect of programming disturbance on the endurance of a non-volatile storage transistor.